The present invention relates to a semiconductor image pickup device provided with an image pickup pixel array. More specifically, this invention relates to a semiconductor image pickup device which sequentially selects pixels based on an X-Y address method and reads the output signal.
FIG. 7 is a schematic block diagram of a conventional semiconductor image pickup device of X-Y address type. This semiconductor image pickup device comprises a pixel array 51 having a plurality of pixels arranged in a matrix, column direction read transistors (a column direction read transistor 58n and the like), column direction reset signal buffers (a column direction reset signal buffer 59n and the like), column direction read control line buffers (a column direction read control line buffer 60n and the like) provided for the respective columns of the pixel array 51, and row direction reset signal buffers (a row direction reset signal buffer 61m and the like) and row direction read control line buffers (a row direction read control line buffer 62m and the like) provided for the respective rows of the pixel arrays 51.
Each pixel in the pixel array 51, e.g., a pixel 52mn in row m and column n (the row m and the column n is an arbitrary matrix number of the pixel array 51) comprises a light detecting element (photodiode) 53mn, a column direction reset transistor 54mn, a row direction reset transistor 55mn, an amplification AMI (Amplified MOS Imager) transistor 56mn and a row direction read transistor 57mn. The column direction reset transistor 54mn is connected to the charge accumulation section of the photodiode 53mn. 
The column direction reset signal buffer 59n receives a column direction reset signal XR2[n] and turns on or off the respective column direction reset transistors (the column direction reset transistor 54mn and the like) in column n depending upon the received signal. The column direction read signal buffer 60n receives a column direction read signal XS2[n] and turns on or off the column direction read transistor 58n depending upon the received signal. The row direction reset signal buffer 61m receives a column direction reset signal YR2[m] and turns on or off the respective row direction reset transistors (the row direction reset transistor 55mn and the like) in row m depending upon the received signal. The row direction read signal buffer 62m receives a column direction read signal YS2[m] and turns on or off the respective row direction read transistors (the row direction read transistor 57mn and the like) in row m depending upon the received signal.
If both the column direction reset transistor 54mn and the row direction reset transistor 55mn are turned on, the voltage of the anode of the photodiode 53mn becomes a photodiode reset power voltage VDC, charges accumulated in the photodiode 53mn are discharged and the photodiode 53mn is turned into a reset state. That is, the pixel 52mn is reset. If both the column direction read transistor 58n and the row direction read transistor 57mn are turned on, a current according to the charges accumulated in the photodiode 53mn flows into the amplification AMI transistor 56mn and is outputted as an output signal. That is, read operation is carried out.
Further, the same power is supplied to the respective pixels (the pixel 52mn and the like), the column direction reset signal buffers (the column direction reset signal buffer 59n and the like), the column direction read signal buffers (the column direction read signal buffer 60n and the like), the row direction reset signal buffers (the row direction reset signal buffer 61m and the like) and the row direction read signal buffers (the row direction read signal buffer 62m and the like).
FIG. 8 is an explanatory view for the operation of the conventional semiconductor image pickup device. In the operation of the semiconductor image pickup device, two pixels on the pixel array 51 are simultaneously read and reset. For example, when a pixel 52qs in row q and column s is reset, a pixel 52pr in row p and column r is simultaneously read. The positions of the pixels to be reset and read move from a row q, column s position and a row p, column r position to a row q, column (s+1) position and a row p, column (r+1) position, respectively. When the reset and read of pixels in rows q and p are completed, reset and read target rows move to rows (q+1) and (p+1). After completing with the last row and column, the reset or read position returns to the leading row and column. In this way, scanning is carried out.
As for each pixel, a time after the pixel is reset until read or, in case of FIG. 8, a time for which the pixel position moves from the row p, column r position to the row q, column s position becomes a charge accumulation time for each photodiode. Namely, during this charge accumulation time, charges are accumulated in the charge accumulation section of the photodiode of each pixel. If both the corresponding row direction read transistor and the corresponding column direction read transistor are turned on, an output signal according to the accumulated charges is outputted.
FIG. 9 is a timing chart showing the operation of the conventional semiconductor image pickup device. In the operation of the conventional semiconductor image pickup device, first, the row direction reset signal YR2[m] is kept turned on (high level) until the resetting of the row m is completed. Then, when the column direction reset signal XR2[n] is turned on (A2 in FIG. 9), the pixel 52mn is reset. Thereafter, the row direction read signal YS2[m] is kept turned on until the read of the row m is completed. When the column direction reading signal XS2[n] is turned on (B2 in FIG. 9), the pixel 52mn is read.
During a charge accumulation time T2, since the pixel 52mn is reset until being read, the row direction reset signal YR2[m] is turned off after the reset selected row is moved to row (m+1), but the column direction reset signal XR2[n] is turned on and off a plurality of times (C2 in FIG. 9). This is because pixels in rows other than the row m and in column n are reset. The number of times the column direction reset signal XR2[n] is turned on and off corresponds to the positional relationship between a reset target row and a read target row. In case of FIG. 8, for example, the column direction reset signal XR2[n] is turned on and off (qxe2x88x92pxe2x88x921) times.
In this way, if the column direction reset signal XR2[n] is turned on and off during the charge accumulation time T2, the column direction reset transistor 54mn is turned on and off and charging and discharging are carried out according to the parasitic capacitance between the gate and substrate of the column direction reset transistor 54mn. Part of charges thus charged and discharged flow into the photodiode 53mn, thereby generating a charge-pumping phenomenon so that the potential of the photodiode 53mn changes. FIG. 10A to FIG. 10C are explanatory views for the charge-pumping operation (charge-pumping phenomenon) of the conventional semiconductor image pickup device.
In the charge-pumping phenomenon of the semiconductor image pickup device, first, the row direction reset signal YR2[m] and the column direction reset signal XR2[n] are turned off (low level), a power supply voltage is applied to the gate control signal line 77 of the column direction reset transistor 54mn by the column direction reset signal buffer 59n, and the column direction reset transistor 54mn is turned off. During the charge accumulation time T2, the row direction reset signal YR2[m] is kept turned off and a current between the p+ source layer 71 and p+ drain layer 72 of the column direction reset transistor 54mn is cut off (see FIG. 10A).
Here, when the column direction reset signal XR2[n] is turned on, the gate control signal line 77 is grounded and the charges (electrons in this example) accumulated in the parasitic capacity between the gate 76 and the p-type silicon substrate 75 of the column direction reset transistor 54mn are discharged to an n-well layer 74 side (see FIG. 10B). Thereafter, when the column direction reset signal XR2[n] is turned off, a power supply voltage is applied again to the gate control signal line 77 and charges are accumulated again in the parasitic capacitance between the gate 76 and the p-type silicon substrate 75. In this charge and discharge process, part of charges flow into the charge accumulation section (p-charge accumulation layer) 73 of the photodiode 53mn (see FIG. 10C). As a result, the potential of the p-charge accumulation layer 73 changes.
FIG. 11 shows how the quantity of accumulated charges of the photodiode 53mn changes with the passage of time in case of the conventional semiconductor image pickup device. As shown in FIG. 11, during the charge accumulation time T2, whenever the column reset signal XR2[n] is turned on or off, the photodiode 53mn has a change in charge accumulation quantity due to the charge-pumping operation. That is, in addition to the charge accumulation by the optical signal from the outside, the charge accumulation by charge pump operation is carried out. The potential variation of the photodiode due to this charge pumping operation is susceptible to process irregularities such as the finished dimensions of the gate of the column direction reset transistor. Due to this, the potential variation differs among the pixels, which is one cause for fixed pattern noise.
Nevertheless, according to the conventional technique, the column direction reset signal buffers control switching gates (column direction reset transistors) connected to the charge accumulation section of the light detecting elements, respectively, while using the power voltage common to the pixel array 51. For that reason, the quantity of charge to be charged and discharged in the charge pumping operation increases, thereby disadvantageously increasing fixed pattern noise.
It is an object of the present invention to obtain a semiconductor image pickup device capable of reducing fixed pattern noise.
The semiconductor image pickup device according to the present invention comprises a switching gate control unit for controlling the switching gate using a lower control power supply voltage than a power supply voltage of the pixel array. This switching gate control unit controls the switching gate connected to the charge accumulation section of the light receiving element using a lower control power supply voltage than the power supply voltage of the pixel array. As a result, the quantity of charges to be charged and discharged in the charge-pumping operation is decreased.
Further, the control power supply voltage is set to be lower than the power supply voltage of the pixel array and to be not lower than a voltage obtained by subtracting the threshold voltage of the transistor in the switching gate control unit turned on if the switching gate is cut off, from the power supply voltage of the pixel array. Because of such arrangement, it is possible to suppress leak current flowing from the light receiving element through the transistor.
Further, a control power supply voltage generation unit is provided for generating the control power supply voltage. Accordingly, it is not necessary to input a control power supply voltage from an external circuit.
Further, the control power supply voltage generation unit is a resistance division circuit dividing the power supply voltage of the pixel array by a plurality of resistors and generating the control power supply voltage. Thus, power consumption can be reduced.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.